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FPGA SIMULATION OF AD CONVERTER BY USING GIGA HERTZ SPEED DATA ACQUISITION FOR PARTIAL DISCHARGE DETECTION This paper is purely a model to determine the design circuit to implement Partial Discharge(PD) detection in FPGA technology. The research involve ISE simulator version 9.2i(Xilinx)and very high integrated circuit Hardware Description Language(VHDL) programming to evaluate the use of Field Programming Gate Array(FPGA)for the detection and counting of partial discharge signals in underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The functional approach of the ADC with peak detector block and counter with reset block will be described and emphasize in this paper. |
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2楼2011-03-03 15:15:39
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