| 查看: 911 | 回复: 3 | |||||||
| 当前只显示满足指定条件的回帖，点击这里查看本话题的所有回帖 | |||||||
[交流]
业内Top3外企-研发岗位招聘-要求学校背景985/211-坐标北京/上海-可先站内私信咨询
|
|||||||
Principal / Lead Front-end Design Engineer (RTL) Location: BJ/SH Position Description: Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies. Specific duties include: Proficiency in logic design, simulation. Proficiency in Verilog and its simulation environment. Good knowledge of IC design. At least seven year experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment. Position Requirements: Essential Qualifications: Must have BS degree with 7~12+ years of applicable experience, MS degree with 5~10+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics. Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English. Will have demonstrated successful completion of 10+ design projects as an individual contributor. Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience. Email: electronics98@126.com |
回复此楼» 猜你喜欢
能否申诉？
已经有3人回复
-
有多少人是今天查系统知道结果的？
已经有19人回复
-
找导师
已经有7人回复
-
售SCI文章，我:8O5.5.1.O.54,科目齐全,可+急
已经有4人回复
-
售SCI一区T0P文章，我:8O.55.1.O.54,科目全,可伽急
已经有5人回复
-
售SCI一区T0P文章，我:8.O.55.1.O.54,科目齐全,可+急
已经有4人回复
-
售SCI一区文章，我:8.O.55.1.O.54,科目齐全,可伽急
已经有6人回复
-
有没有仍没收到信息的
已经有7人回复
-
国社科又开始会评了，不知道这次命运如何
已经有4人回复
-
售SCI文章，我:8O5.5.1.O.54,科目齐全,可+急
已经有8人回复
4楼2018-10-03 22:25:35
2楼2018-10-02 21:54:19
3楼2018-10-03 03:35:56
10