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Lolita*@

新虫 (初入文坛)

应助: 0 (幼儿园)
金币: 359
帖子: 42
在线: 34.4小时
虫号: 8011668
注册: 2018-02-11
性别: MM
专业: 教育学原理

上海-可先站内私信咨询

具体工作地点:

北京东城区/上海浦东新区

薪金:

800K/Y

Principal / Lead Front-end Design Engineer (RTL)
Location: BJ/SH
Position Description:
Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies.
Specific duties include:
Proficiency in logic design, simulation.
Proficiency in Verilog and its simulation environment.
Good knowledge of IC design.
At least seven year experience working on digital IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
Position Requirements:
Essential Qualifications: Must have BS degree with 7~12+ years of applicable experience, MS degree with 5~10+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
Essential that the individual demonstrates strong communication, verbal and written.
Requires good communication skills in English.
Will have demonstrated successful completion of 10+ design projects as an individual contributor.
Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience.

Email: electronics98@126.com

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