| 查看: 995 | 回复: 2 | ||
[求助]
为什么我的的vhdl三个程序都出现这个错误呢？
|
|
library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity top is port ( clk1:in std_logic; C1,C5,P2,P3:in std_logic; pay_lcd0,pay_lcd1,need_lcd0,need_lcd1,Mout_lcd0,Mout_lcd1  utstd_logic_vector(6 downto 0); s,f,showout ut std_logic  ;end top; architecture one of top is component fanmaijioriginal port( clk:in std_logic; coin1:in std_logic; coin5:in std_logic; select2:in std_logic; select4:in std_logic; pay ut std_logic_vector(3 downto 0);need ut std_logic_vector(3 downto 0); success ut std_logic;failure ut std_logic; getready ut std_logic; change ut std_logic_vector(3 downto 0) ; end component; component code11 port( b:in std_logic_vector(3 downto 0); b1 ut std_logic_vector(3 downto 0); b2 ut std_logic_vector(3 downto 0) ); end component; component code12 port( b:in std_logic_vector(3 downto 0); b1 ut std_logic_vector(3 downto 0); b2 ut std_logic_vector(3 downto 0) ); end component; component code13 port( b:in std_logic_vector(3 downto 0); b1 ut std_logic_vector(3 downto 0); b2 ut std_logic_vector(3 downto 0) ); end component; component code21 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0)); end component; component code22 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0)); end component; component code23 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0)); end component; component code24 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0));end component; component code25 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0)); end component; component code26 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0));end component; signal p,n,mo:std_logic_vector(3 downto 0); signal s1,s2,s3,s4,s5,s6:std_logic_vector(3 downto 0); begin u0:fanmaiji port map (clk=>clk1,coin1=>C1,coin5=>C5,select2=>P2,select4=>P3,success=>s, failure=>f,getready=>change,pay=>p,need=>n,change=>mo); u1:code11 port map(b=>p,b1=>s1,b2=>s2); u2:code12 port map(b=>n,b1=>s3,b2=>s4); u3:code13 port map(b=>mo,b1=>s5,b2=>s6); u4:code21 port map(d=>s1,q=>pay_lcd0); u5:code22 port map(d=>s2,q=>pay_lcd1); u6:code23 port map(d=>s3,q=>need_lcd0); u7:code24 port map(d=>s4,q=>need_lcd1); u8:code25 port map(d=>s5,q=>Mout_lcd0); u9:code26 port map(d=>s6,q=>Mout_lcd1); end one; 错误：Error (10500): VHDL syntax error at code2.vhd(2) near text "libraryÂ"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration" |
回复此楼» 猜你喜欢
今年审到国自然15份，谈谈感受
已经有20人回复
-
Sci. Bull. 悲剧经验
已经有5人回复
-
国自然评分
已经有4人回复
-
提交了我也来说说感想
已经有4人回复
-
面上本子正文33页，违规吗？会被低分嘛？
已经有11人回复
-
评审有感
已经有22人回复
-
反应很差，大量原料没有反应
已经有6人回复
-
如果工作了想读博，可以边工作边读全日制嘛？
已经有5人回复
-
如何实现卤原子转化
已经有8人回复
-
河北省自然科学基金
已经有3人回复
|
library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity top is port ( clk1:in std_logic; C1,C5,P2,P3:in std_logic; pay_lcd0,pay_lcd1,need_lcd0,need_lcd1,Mout_lcd0,Mout_lcd1 utstd_logic_vector(6 downto 0); s,f,showout ut std_logic ;end top; architecture one of top is component fanmaijioriginal port( clk:in std_logic; coin1:in std_logic; coin5:in std_logic; select2:in std_logic; select4:in std_logic; pay ut std_logic_vector(3 downto 0);need ut std_logic_vector(3 downto 0); success ut std_logic;failure ut std_logic; getready ut std_logic; change ut std_logic_vector(3 downto 0) ; end component; component code11 port( b:in std_logic_vector(3 downto 0); b1 ut std_logic_vector(3 downto 0); b2 ut std_logic_vector(3 downto 0) ); end component; component code12 port( b:in std_logic_vector(3 downto 0); b1 ut std_logic_vector(3 downto 0); b2 ut std_logic_vector(3 downto 0) ); end component; component code13 port( b:in std_logic_vector(3 downto 0); b1 ut std_logic_vector(3 downto 0); b2 ut std_logic_vector(3 downto 0) ); end component; component code21 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0)); end component; component code22 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0)); end component; component code23 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0)); end component; component code24 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0));end component; component code25 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0)); end component; component code26 port( d:in std_logic_vector(3 downto 0); q ut std_logic_vector(6 downto 0));end component; signal p,n,mo:std_logic_vector(3 downto 0); signal s1,s2,s3,s4,s5,s6:std_logic_vector(3 downto 0); begin u0:fanmaiji port map (clk=>clk1,coin1=>C1,coin5=>C5,select2=>P2,select4=>P3,success=>s, failure=>f,getready=>change,pay=>p,need=>n,change=>mo); u1:code11 port map(b=>p,b1=>s1,b2=>s2); u2:code12 port map(b=>n,b1=>s3,b2=>s4); u3:code13 port map(b=>mo,b1=>s5,b2=>s6); u4:code21 port map(d=>s1,q=>pay_lcd0); u5:code22 port map(d=>s2,q=>pay_lcd1); u6:code23 port map(d=>s3,q=>need_lcd0); u7:code24 port map(d=>s4,q=>need_lcd1); u8:code25 port map(d=>s5,q=>Mout_lcd0); u9:code26 port map(d=>s6,q=>Mout_lcd1); end one; 这是程序，上面那个不知道怎么出那么多表情。。。。 |
2楼2017-03-20 12:33:12
cdeda
至尊木虫 (知名作家)
- 应助: 1 (幼儿园)
- 金币: 17375.1
- 红花: 1
- 沙发: 8
- 帖子: 5228
- 在线: 133.2小时
- 虫号: 1239617
- 注册: 2011-03-20
- 性别: GG
- 专业: 信息理论与信息系统
3楼2017-03-20 17:23:35
5