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yyzhao2013

新虫 (初入文坛)

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在线: 1小时
虫号: 5811057
注册: 2017-03-02

[求助] 为什么我的的vhdl三个程序都出现这个错误呢？

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity top is
port (
clk1:in std_logic;
C1,C5,P2,P3:in std_logic;
pay_lcd0,pay_lcd1,need_lcd0,need_lcd1,Mout_lcd0,Mout_lcd1

utstd_logic_vector(6 downto 0);
s,f,showout

ut std_logic

;
end top;
architecture one of top is component fanmaijioriginal
port( clk:in std_logic;
coin1:in std_logic;
coin5:in std_logic;
select2:in std_logic;
select4:in std_logic;
pay

ut std_logic_vector(3 downto 0);
need

ut std_logic_vector(3 downto 0);
success

ut std_logic;
failure

ut std_logic;
getready

ut std_logic;
change

ut std_logic_vector(3 downto 0)

;
end component;
component code11
port(
b:in std_logic_vector(3 downto 0);
b1

ut std_logic_vector(3 downto 0);
b2

ut std_logic_vector(3 downto 0)
);
end component;
component code12
port( b:in std_logic_vector(3 downto 0);
b1

ut std_logic_vector(3 downto 0);
b2

ut std_logic_vector(3 downto 0)
);
end component; component code13
port(
b:in std_logic_vector(3 downto 0);
b1

ut std_logic_vector(3 downto 0);
b2

ut std_logic_vector(3 downto 0)
);
end component;
component code21
port(
d:in std_logic_vector(3 downto 0);
q

ut std_logic_vector(6 downto 0)
);
end component;
component code22
port(
d:in std_logic_vector(3 downto 0);
q

ut std_logic_vector(6 downto 0));
end component;
component code23
port(
d:in std_logic_vector(3 downto 0);
q

ut std_logic_vector(6 downto 0)
);
end component;
component code24
port(
d:in std_logic_vector(3 downto 0);
q

ut std_logic_vector(6 downto 0));
end component;
component code25
port(
d:in std_logic_vector(3 downto 0);
q

ut std_logic_vector(6 downto 0));
end component;
component code26
port(
d:in std_logic_vector(3 downto 0);
q

ut std_logic_vector(6 downto 0));
end component;
signal p,n,mo:std_logic_vector(3 downto 0);
signal s1,s2,s3,s4,s5,s6:std_logic_vector(3 downto 0);
begin
u0:fanmaiji
port map
(clk=>clk1,coin1=>C1,coin5=>C5,select2=>P2,select4=>P3,success=>s,
failure=>f,getready=>change,pay=>p,need=>n,change=>mo);
u1:code11 port map(b=>p,b1=>s1,b2=>s2);
u2:code12 port map(b=>n,b1=>s3,b2=>s4);
u3:code13 port map(b=>mo,b1=>s5,b2=>s6);
u4:code21 port map(d=>s1,q=>pay_lcd0);
u5:code22 port map(d=>s2,q=>pay_lcd1);
u6:code23 port map(d=>s3,q=>need_lcd0);
u7:code24 port map(d=>s4,q=>need_lcd1);
u8:code25 port map(d=>s5,q=>Mout_lcd0);
u9:code26 port map(d=>s6,q=>Mout_lcd1);
end one;

错误：Error (10500): VHDL syntax error at code2.vhd(2) near text "libraryÂ"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"

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