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hithappy

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[交流] ICMIA 2013 桂林会议的论文全部检索啦。恭喜! 已有7人参与

ICMIA 2013 桂林会议的论文全部检索啦,恭喜,不错的会议。
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thwei2008

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小木虫: 金币+0.5, 给个红包,谢谢回帖
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3楼: Originally posted by tigeer at 2013-09-13 08:39:56
AMM336-338检索了我的已查到被EI收录。

你好,我跟你是一样的,AMM336-338,能帮我查一下我论文的收录情况吗?我的论文题目:32-bit Datapath AES IP Core Based on FPGA谢谢!
4楼2013-09-14 21:00:13
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tigeer

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AMM336-338检索了我的已查到被EI收录。

[ Last edited by tigeer on 2013-9-13 at 11:08 ]
3楼2013-09-13 08:39:56
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tigeer

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我也是在论坛帖查的。有好多好心人帮忙。
5楼2013-09-14 21:45:41
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ght1102

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4楼: Originally posted by thwei2008 at 2013-09-14 21:00:13
你好,我跟你是一样的,AMM336-338,能帮我查一下我论文的收录情况吗?我的论文题目:32-bit Datapath AES IP Core Based on FPGA谢谢!...

Accession number:       
20133516681707
        Title:        32-bit datapath AES IP core based on FPGA
        Authors:         Tang, Hong Wei1
        Author affiliation:        1 Shaoyang University, Shaoyang, China
        Corresponding author:         Tang, H. (thwei2008@126.com)
        Source title:        Applied Mechanics and Materials
        Abbreviated source title:        Appl. Mech. Mater.
        Volume:        336-338
        Monograph title:        Industrial Instrumentation and Control Systems II
        Issue date:        2013
        Publication year:        2013
        Pages:        1848-1851
        Language:        English
        ISSN:         16609336
        E-ISSN:         16627482
        ISBN-13:         9783037857519
        Document type:        Conference article (CA)
        Conference name:        2013 2nd International Conference on Measurement, Instrumentation and Automation, ICMIA 2013
        Conference date:        April 23, 2013 - April 24, 2013
        Conference location:        Guilin, China
        Conference code:         99007
        Sponsor:        Korea Maritime University; Hong Kong Industrial Technology Research Centre; Inha University
        Publisher:        Trans Tech Publications Ltd, Kreuzstrasse 10, Zurich-Durnten, CH-8635, Switzerland
        Abstract:        This paper presents an architecture for 32-bit datapath Advanced Encryption Standard(AES) IP core based on FPGA. It uses finite state machine, and supports encryption, decryption and key expansion. The round-key is calculated before the beginning of encryption and decryption. It consumes less hardware resources. It is implemented on Cyclone II FPGA EP2C35F672C6, which consumes less than 55% logic elements of the resources. The IP core can operate at a maximum clock frequency of 100 MHz. Compared with 128-bit datapath AES, it can interface with CPU easily. © (2013) Trans Tech Publications, Switzerland.
        Number of references:        4
        Main heading:         Cryptography
        Controlled terms:         Data privacy  -  Field programmable gate arrays (FPGA)  -  Storms
        Uncontrolled terms:         Advanced Encryption Standard  -  CAN interface  -  Clock frequency  -  Encryption and decryption  -  Hardware resources  -  IP core  -  Key expansion  -  Logic elements
        Classification code:         443.3 Precipitation -  716 Telecommunication; Radar, Radio and Television -  717 Optical Communication -  718 Telephone Systems and Related Technologies; Line Communications -  721.3 Computer Circuits -  723 Computer Software, Data Handling and Applications
        DOI:        10.4028/www.scientific.net/AMM.336-338.1848
        Database:        Compendex
                Compilation and indexing terms, © 2013 Elsevier Inc.

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