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[½»Á÷] PhD position in LIRMM(CNRS/Unuversity of Montpellier 2) ÒÑÓÐ2È˲ÎÓë

PhD Topic: Circuit and Architectural-Level Power Modeling and Estimation
One of the major concerns in integrated systems design is power management and minimization. Traditional power estimation methods applied at gate level are accurate but slow whereas at architectural level fast and inaccurate. Moreover, performance-over-power tradeoff techniques can no longer ensure reliable circuits, as they are inadequate to address increasing leakage power of scaled technologies.


The objective of this PhD thesis is to investigative power modeling and estimation techniques applicable from circuit to architectural level for ensuring coherency on power estimation and early detection of power hungry blocks throughout the design flow. First phase of the thesis will be focused on development of accurate and hybrid power models. Second phase of the thesis will be focused on development of efficient power estimation techniques that can be applicable at every step of the design flow in order to meet design power constraints.


PhD research will be performed in collaboration with academic and industrial partners that will provide scientific and technical support throughout this thesis.


Keywords: Power modeling and estimation


The following skills and qualifications are useful : - background in electrical engineering with emphasis on VLSI design - prior experience on transistor/block/chip level circuit design, simulation and analysis - prior experience with timing and electrical analysis tools including Spice - prior experience with programming languages i.e. C++, VHDL

Starting Date / Duration: March 2013 / 3 years

If interested in this PhD topic, please send an email with your resume and cover letter to todri@lirmm.fr


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