| 查看: 245 | 回复: 0 | ||
| 当前主题已经存档。 | ||
[资源]
【共享】【书籍】Verilog Coding for Logic Synthesis
|
||
|
Verilog Coding for Logic Synthesis Posted by admin under Science And Engineering Provides a practical approach to Verilog design and problem solving. * Bulk of the book deals with practical design problems that design engineers solve on a daily basis. * Includes over 90 design examples. * There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification. * Book is suitable for use as a textbook in EE departments that have VLSI courses http://www.icefile.net/index.php ... hesis.ebook-Spy.pdf or http://depositfiles.com/files/358765 or http://rapidshare.com/files/2181 ... hesis.ebook-Spy.pdf |
回复此楼» 猜你喜欢
有时候真觉得大城市人没有县城人甚至个体户幸福
已经有3人回复
-
CSC & MSCA 博洛尼亚大学能源材料课题组博士/博士后招生｜MSCA经费充足、排名优
已经有5人回复
-
酰胺脱乙酰基
已经有8人回复
-
有70后还继续奋斗在职场上的吗？
已经有6人回复
-
博士延得我，科研能力直往上蹿
已经有7人回复
-
退学或坚持读
已经有27人回复
-
面上基金申报没有其他的参与者成吗
已经有5人回复
-
遇见不省心的家人很难过
已经有22人回复