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[求助] 英翻汉

A transparent substrate (either a pyrex or quartz wafer) was
prepared by piranha cleaning, and a dehydration bake as
described above. After coating the wafer with resist (SU-8
(50) at 500 rpm for 15 s, followed by 3000 rpm for 15 s), we
soft-baked the resist partially on a hot plate. The temperature
of the hot plate was ramped from room temperature to 105 ◦C
over ～8 min, held at 105 ◦C for 10 min, and then allowed to
cool to ～75 ◦C. We then immediately brought this layer of
SU-8 into contact with a wafer bearing the multilayered SU-8
structures that we had formed. Prior to contact, the second
wafer had been placed on a hot plate at 75 ◦C. As the wafers
were contacted, we applied pressure with a pair of tweezers to
ensure that therewas contact over the majority of thewafer and
that air bubbles were eliminated. After the wafer had cooled to
room temperature, blanket exposure of the resist through the
pyrex wafer and a post-bake schedule as described previously
(ramp up to 105 ◦C, hold at 105 ◦C for 15 min, cool down to
room temperature) produced a sealed microstructure in SU-8.
In cases where we had created fluidic ports in the first
layer of SU-8 (rather than in the substrate), we released the
microstructure from the substrate by placing the devices (oneby-
one) into water and sonicating. The device separated from
the oxide-coated silicon substrate, but remained attached to the
pyrex support.
If fluidic ports already existed in the top wafer (e.g. drilled
quartz wafers), we modified the bonding procedure. The
quartz/SU-8 devices were fabricated by first preparing the two
quartz wafers (both the one with holes drilled and without)
as described above. We then coated the undrilled wafer with
SU-8 (50) to form a film approximately 50 μm thick. The prebake
procedurewas as for bonding otherwafers with SU-8: the
resist was ramped up to 105 ◦C (over ～8 min), held at 105 ◦C
for 10 min, and then cooled to 75 ◦C, at which point the drilled
wafer was brought into contact with the film of SU-8, pressed
to seal, and cooled down to room temperature. We exposed
the resist through an appropriate mask aligned to the drilled
ports. After the post-exposure bake, the resist was developed
by flowing PGMEA in through the fluidic ports.

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