| 查看: 1255 | 回复: 2 | |||||||
[交流]
帮朋友招聘——硅谷数模半导体有限公司
|
职位 1:Sr. AE x 2名 工作职责: 1. Work with marketing and development teams to define key product features during the product requirement definition; 2. Lead product validation and alpha customer roll out. Create validation plans, track issues from discovery to closure; 3. Develop system level workarounds, define errata, analyze defects and propose remedies; 4. Lesson and Learn management. 职位要求: 1. 7 years’ experience in semiconductor industry; 2. International work experience in a world class supplier or customer; 3. Experience in display or graphics preferred; 4. Experienced as a project lead preferred; 5. Strong system level debugging skill a must; 6. Able to read and analyze C-code, comfortable creating small programs in C-code; 7. Able to develop schematic and review PCB; 8. Strong communication skills, ability to articulate complex issues; 9. Good documentation skills 职位 2: Sr. Firmware Engineer x 1名 工作职责: 1. Development/maintain the embedded firmware at product level (not just for chip companies); 2. Create a world class code base, set example for all release management process. 职位要求: 1. BS or above degree in EE, CE , CS or equivalent, 2. Fluent written and speaking English 3. Embedded firmware experience at product level. 4. Hardware skills(schematic read, oscilloscope, millimeter) are required. 5. Experience on 51 program. 6. IC company experience is preferred. 7. Be good at c/c++ , experienced to use code management tools(svn etc) 职位 3: Sr. Software Engineer x 1名 工作职责: Develop/main tools and create pre-integrated solution in windows/android 职位要求: 1. Expert on C/C++, windows development(SDK/DDK); 2. Be good at visual c++, c#, visual basic etc.; 3. Experienced on android; 4. Experience for code management tools like svn etc. Digital Design Team: 职位 1:Sr. Digital IC Design Engineer x 1名 工作职责: 1. Responsible for architecture definition according to product specifications; 2. Logic design & implementation by Verilog on module level, and chip integration; 3. Design synthesis, timing analysis, DFT and ATPG; 4. Work closely with backend engineer for chip tape-out; 5. Work closely with application engineer for chip bring-up, debug and solve problem. 职位要求: 1. Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering and Computer Science; 2. At least 2+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA.; 3. Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC and PrimeTime.; 4. Familiar with cryptosystem such as RSA/AES is a big plus; 5. Familiar with FPGA prototyping is a big plus; 6. Familiar with mixed signal design is a big plus; 7. Good written and oral English communication skills. 如果有合适的同学,请把简历发到121630448@qq.com 关于待遇和其他的福利问题,请具体和他联系。谢谢! |
» 猜你喜欢
求各位大神看下
已经有15人回复
【2027博士申请】纳米药物递送方向
已经有4人回复
8月时间戳变的,举个手。玩一下,释放压力
已经有6人回复
面上再次挂了,太难了,躺也躺不了,倦也卷不过,小学校之殇!
已经有29人回复
UV压敏胶开发
已经有7人回复
有没有H口的?有收到消息的吗?
已经有3人回复
十年后又回来了,论文投稿求助
已经有3人回复
纯娱乐,不喜欢勿喷
已经有10人回复
面上提前没消息,有中的吗
已经有18人回复
娱乐
已经有4人回复
|
祝福 [ 发自手机版 http://muchong.com/3g ] |
2楼2015-01-27 15:52:25
| 祝福 |
3楼2015-01-27 20:13:35










回复此楼