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bravexy

木虫 (小有名气)

应助: 0 (幼儿园)
金币: 2203.8
帖子: 261
在线: 56.8小时
虫号: 1652584
注册: 2012-02-29
专业: 光子与光电子器件

[求助] 谁能写一下AD7888的verilog的注释

以下是AD7888 verilog驱动程序，我看不太懂，哪位大神能写一下注释，写一些主要的注释也行啊！急用，跪谢！
module ad7888 (CS,CLKin,CLKout,DIN,DOUT,DATA,test);

input  CLKin;
input DOUT;
output reg DIN,CS,CLKout,test;
output[15:0] DATA;
//reg i,j;
wire DOUT;
reg start;
//reg[7:0] Strdatah;
//reg[7:0] Strdatal;
//reg[7:0] Tempdata;
reg[4:0] state,NS;
//reg Adcaddres[0:7];
reg[15:0] DATA,data;
reg [5:0] count_50x;
parameter
IDLE=5'b00001,S1=5'b00010,S2=5'b00011,S3=5'b00100,S4=5'b00101,S5=5'b00110,S6=5'b00111,S7=5'b01000,
S8=5'b01001,S9=5'b01010,S10=5'b01011,S11=5'b01100,S12=5'b01101,S13=5'b01110,S14=5'b01111,S15=5'b10000,
S16=5'b10001,S17=5'b10010,S18=5'b10011,S19=5'b10100;
initial
begin
//i=0;
//j=0;
//Strdatah=0;
//Strdatal=0;
//Tempdata=0;
NS=IDLE;
start=0;
data=16'b0000000000000000;
state=5'b00000;
CS=1;
DATA=16'b0000111111111111;
test=1;
end
///*
//内部时钟50分频
// 上升沿计数: 0~(N-1)
always @ (posedge CLKin)
begin

if (count_50x == 49)
   count_50x <= 0;
else
   count_50x <= count_50x + 1'b1;

end

// 生成上升沿时钟
// 0~(N/2-1) ↑ -> 1; (N/2)~(N-1) ↑ -> 0
always @ (posedge CLKin)
begin

if (count_50x <= 24)

   CLKout <= 1;
else
   CLKout<= 0;

end

always @ (posedge CLKout)
//begin state<=NS; end

//always @(posedge )
  case(NS)
  IDLE:  begin NS<=S1; CS<=1;  end
  S1: begin NS<=S2; CS<=0; start<=1; end
  S2: begin NS<=S3; DIN<=0;  end
  S3: begin NS<=S4; DIN<=0; end
  S4: begin NS<=S5; DIN<=0; end
  S5: begin NS<=S6; DIN<=0; end
  S6: begin NS<=S7; DIN<=0; end
  S7: begin NS<=S8; DIN<=0; end
  S8: begin NS<=S9; DIN<=0; end
  S9: begin NS<=S10;DIN<=0; end
  S10: begin NS<=S11; end
  S11: begin NS<=S12; end
  S12: begin NS<=S13; end
  S13: begin NS<=S14; end
  S14: begin NS<=S15; end
  S15: begin NS<=S16; end
  S16: begin NS<=S17; end
  S17: begin NS<=S18;end
  S18: begin NS<=S19; start<=0;  end
  S19: begin NS<=IDLE;DATA<=data;CS<=1; end
  default:begin NS<=IDLE;  end
  endcase

always @(negedge CLKout)
begin
case(start)
1: begin data<={data[14:0],DOUT}; end //test<=1;
0:;
default:;
endcase
end
//*/
endmodule

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