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PID效应文献翻译 能有全文的翻译最好了
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One mechanism of degradation associated with system bias is polarization, whereby current through the front glass leads to accumulation of trapped charge over the active layer. This charge can influence the surface field of the semiconductor active layer [2]. In severe cases, accumulation of mobile ions, such as Na, leads to delamination when the active layer is biased negatively [4,12]. In mc-Si modules, PID associated with a negatively biased active layer also leads to positive ions such as Na moving from the glass toward the active layer, but the observed cell shunting that results speculatively suggests incorporation of deleterious ions in the active layer [7]. Modules made of packaging materials that leak almost no current to ground, such as quartz front window layers and resistive thermoplastic encapsulants, do not degrade under system bias stress tests [13]. Material properties on the cell level that modulate the extent of PID have also been previously analyzed [6]. Usually in the presence of elevated humidity within the module, degradation by electrolytic corrosion occurs and macroscopic transport of ionized conductor metal may be observed [13-16]. In all these cases, current flow involving ionic motion in some part of the circuit between the high-voltage active layer of the module to ground is involved. There are publications showing how module leakage current to ground increases with environmental chamber temperature and relative humidity (RH) for samples designed to test for electrolytic corrosion [14-16] and with commercial modules [13]. Relationships between the accumulated leakage current and module power degradation were also shown. We need to determine stress factors and levels for a test of modules’ durability to system voltage that will serve the needs of materials and component makers, module makers, and PV customers. To do so, we must understand further the active degradation mechanisms and how they vary according to stress factors such as temperature, humidity, and bias. With this understanding, we can ensure that the stress levels for each factor are representative and reasonable to carry out in consideration of cost, time, and effectiveness to evaluate modules’ resistance to system voltage degradation. In this paper, we evaluate the environmental conditions that factor into system voltage-induced degradation mechanisms. Considering these, we discuss the accelerated stress tests and suitable levels that reproduce the field-observed PID. We report on chamber step stress tests performed on mc-Si mini-modules to evaluate the relationship between level of stress and PID. This is followed by an analysis of acceleration factors as a function of temperature using leakage current measured in fielded modules as a basis and a discussion of the strategies and limitations for accelerated lifetime testing for PID. Finally, an evolving model for PID degradation is discussed. |
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2013-04-29 01:37:11, 989.85 K
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