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always @(posedge clk) begin

       if(!rst_n)

              state        <= idle;

       else

              state        <= next_state;

end

always @(state) begin

       case(state)

              s0:   begin

                     //

                     out1        =   ;

                     out2     =    ;

                     next_state      =     ;

                     //

              end

              s1:   begin

                     //

                     out1        =   ;

                     out2     =    ;

                     next_state      =     ;

                     //

              end

       endcase

end

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yinqingwang

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songwenhua

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