| 查看: 353 | 回复: 2 | |||
[交流]
【AMD】上海logic design team内部推荐
|
|
大家好，我是AMD上海研发中心logic design team的工程师。我们部门现在对外开放2个招聘名额，有兴趣的童鞋请把简历发至joe.li@amd.com 在这里，你能接触到graphic core里面最核心的设计。 以下是JD： Design Engineer (MTS) Responsibility: • Develop micro-architecture for GPU blocks based on architectural requirement. • Develop RTL code for GPU blocks in Verilog HDL and make sure functional correct and reusable for different configuration. • Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing. Requirement: • MS degree of EE with 5+ years working experience in ASIC Company. • Expert of Verilog RTL design and has experience of large digital ASIC project. • Familiar with front-end EDA tools and flows. • Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.) • Fluent English on talking, presentation and writing documents. • Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager. • Can solves complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation • Possesses specialized knowledge of Computer architecture and computer arithmetic (a plus) • Possesses specialized knowledge of Computer graphic knowledge (a plus) Design Engineer (Sr. Eng) Responsibility: • Develop micro-architecture for GPU blocks based on architectural requirement. • Develop RTL code for GPU blocks in Verilog HDL and make sure functional correct and reusable for different configuration. • Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing. Requirement: • MS degree of EE with 3+ years working experience in ASIC Company. • Familiar with Verilog RTL design and has experience of digital ASIC project. • Familiar with front-end EDA tools and flows. • Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.) • Fluent English on talking, presentation and writing documents. • Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager. • Possesses specialized knowledge of Computer architecture and computer arithmetic (a plus) Design Engineer (NCG -> Eng2) Responsibility: · Develop micro-architecture specification for GPU blocks. · Develop RTL code for GPU blocks in Verilog HDL. · Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design. · Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology. Requirement: · Master or above degree. · Major in Micro-E or related, Electronic Engineer, Computer Science, Mathematics. Communication. · Familiar with Verilog HDL coding and ASIC Frond-End implementation flow. · Familiar with unix/linux and scripts (tcl, perl, python etc.). · Strong task-based organization skills. · Computer architecture and computer arithmetic (a plus). · Computer graphic basic knowledge (a plus). · Experience with Database technologies and database-driven custom web application development (a plus). · Proficient English and Mandarin (listening, writing and speaking). · Have project experience during university education. · Strong passion in achievement and career development. · A self-motivated team player. |
回复此楼» 猜你喜欢
一志愿厦大0856，306求调剂
已经有8人回复
-
269求调剂
已经有11人回复
-
366求调剂
已经有7人回复
-
268求调剂
已经有5人回复
-
药学专硕调剂
已经有8人回复
-
271求调剂
已经有7人回复
-
290调剂生物0860
已经有9人回复
-
求调剂
已经有6人回复
-
283求调剂 086004考英二数二
已经有18人回复
-
0854调剂
已经有5人回复
2楼2012-05-07 22:52:18
3楼2012-06-04 21:37:23
