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[交流] 卢森堡大学Software-Defined Vehicle方向招聘优秀博士生 (全额奖学金)

欢迎感兴趣的同学通过学校网站申请: https://recruitment.uni.lu/en/details.html?id=qmufk026203f3vbqb7v7vv4s8&npostingid=65336&npostingtargetid=93990&mask=karriereseiten&lg=uk

研究课题
Software has been playing a prominent role in vehicle for many years now, as a large majority of the functions of a vehicle are mostly implemented in software. Some of next generation’s electronic control units (ECUs) will be equipped with powerful system-on-chips (SoCs), each containing several multicore processors with specific capabilities (e.g., lock-step execution for safety-critical code, low-power execution, etc). Larger ECUs routinely support hypervisors hosting virtual machines (VM) running OSes of different types (e.g., real-time, infotainment or general-purpose os). Besides VMs, software containers are also technologies that start being considered for use in the automotive domain to ease software update.

In that landscape, a new trend is that the runtime execution platform increasingly relies on software, allowing for more modularity and providing a lot of flexibility in terms of configuration, or re-configuration after new functions have been deployed. For instance, software components executing in the VMs may communicate through software-implemented (“virtual”) network interfaces connected to a virtual ethernet switch, i.e. software replacing the actual HW. More generally, what has been observed over the last decade is that the complexity is migrating from the hardware (in the past, vehicles sometimes had 50+ ECUs, most running a few functions) to the software (today E/E architectures tend to rely on a lesser number of powerful ECUs, with complex internal software architectures). This era of increasing reliance on software in the automotive domain is referred to as Software-Defined Vehicle (SDV).

If SDV holds much promises, it requires us to rethink the existing design, development and verification approaches:
- SDV may require more software-centric design and development methodologies.
- additional run-time mechanisms, e.g. implemented in middleware software layers, may be needed to complement current standards and technologies.
- configuration and design-space-exploration (DSE) algorithms need to be extended to support SDV.
- performance evaluation in the automotive domain is typically conducted with worst-case scheduling analysis (“schedulability analysis”) at the level of a processor or at system level (considering “timing chains” over different processors and networks). Are the existing techniques, such as system-level compositional analysis, able to cope with the complexity of next-generation execution platforms? If not, what would be the techniques that could allow verifying that non-functional concerns like timing and safety are met?

This phd thesis explores these questions with the aim to contribute to the design of provably-correct SDV E/E architectures.

导师:
Prof. Nicolas Navet
https://wwwfr.uni.lu/recherche/fstm/dcs/membres/nicolas_navet
https://nicolas.navet.eu/

申请要求:
- master’s degree in computer science or electrical engineering,
- ideally, some background in embedded systems, networking and model-based design,
- strong analytical capacities, creativity and commitment,
- good programming skills,
- good written and oral english skills.

合同类型:
- contract type: fixed term contract 36 month - extendable up to 48 months if required
- work hours: full time 40.0 hours per week
- earliest starting date: September 2021
- location: Belval, Luxembourg
- employee and student status

如何申请:
Applications in english should include:
- a motivation letter, with a clear statement of interest for the position,
- a detailed curriculum vitae,
- a transcript of the grades you received in your bachelor and master studies,
- an abstract of your master thesis with a download link,
- the names and contact details of two referees.

Applications sent by e-mail will not be considered; please apply ONLINE through the university recruitment website.

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