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[求助]
用Verilog 写的SDRAM控制器实现读写功能，没出现像，求帮忙看看，多谢。
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module sdram_0 ( // input reset, clk, in_data, //full,empty, // out addr, bank,//??????????????????????????????????????? cas, cke, cs, dq,// yu za_data qu bie ?????????????????? dqm, ras, out_data, we, ); // duan kou sheng ming input reset,clk; input [40:0]in_data;//addr [37:16] data[15:0] output [11:0] addr; reg [11:0] addr; output reg [1:0] bank; output cas,cke,cs,ras,we; wire cas,cke,cs,ras,we; assign cke=1'b1; wire [3:0] cmd; assign{cs,ras,cas,we}=cmd; assign cmd=init_done?m_cmd:i_cmd; inout [15:0] dq; wire [15:0] dq; output [1:0] dqm; wire [1:0] dqm; assign dqm=2'b00; output reg [15:0] out_data; reg init_done; // ji shu ji cun qi sheng ming reg [15:0]NOP_counter; //200 us and 8 us auto refresh // kong zhi ji cun qi ; reg ref_req; reg [3:0] i_cmd; reg [11:0] i_addr; reg [2:0] counter; reg [2:0] i_state; reg [2:0] i_next; reg r; reg [99:0]rr; reg start; always @ (posedge clk or negedge reset ) begin if(reset==0) begin NOP_counter<=19200; ref_req<=0; rr<=0; start<=1; end else begin if(NOP_counter==1) begin ;NOP_counter<=800;if(rr==0) begin rr<=rr+1; start<=1; end else start<=0;end else begin NOP_counter<=NOP_counter-1; end ref_req <= ((NOP_counter == 1) | ref_req) & ~act_ref_req & init_done; end end always@(posedge clk or negedge reset ) begin if(reset==0) begin i_addr<={12{1'b1}}; counter<=0; i_state<=3'b000; i_next<=3'b000; r<=0; end else if(!init_done && (start==0)) case(i_state) // qu xiao xin pian 3'b000: begin i_cmd<=4'b1111;i_state<=3'b001;end // precharge 3'b001: begin i_cmd<=4'b0010;i_state<=3'b011;i_next<=3'b010;end //auto_charge 3'b010:begin i_cmd<=4'b0001;i_state<=3'b011;counter<=3; if(r<1) begin i_next<=2; r<=r+1;end else i_next<=7; end //NOP 3'b011:begin i_cmd<=4'b0111; if(counter > 1) counter<=counter-1; else i_state<=i_next; end // 3'b101:begin i_state<=3'b101; end // mo shi she ding 3'b111:begin i_cmd<=4'b0000; i_state<=3'b011; i_next<=3'b101; counter<=4;i_addr={12{1'b0}}; end default :i_state<=3'b000; endcase end always @(posedge clk or negedge reset) begin if(reset==0) init_done<=0; else if(i_state==5) init_done<=1; end // work state // 3 22 16 assign {m_wor,m_bus_addr,m_data}=in_data; wire [2:0] m_wor; // read or write signal wire wr ; assign wr={m_wor[0]}; wire [21:0] m_bus_addr; // addr bus assign m_bank={m_bus_addr[21],m_bus_addr[8]};///////********************** you wen ti wire [11:0] m_addr; // addr wire [15:0] m_data; // data wire [1:0] m_bank; reg [2:0]m_count; reg [3:0] m_state; reg [3:0] m_next; reg [3:0] m_cmd; reg oe; reg act_ref_req; // 1 active assign dq=oe? m_data:16'bzzzz; always @(posedge clk ) begin if(reset==0) begin m_state<=0; m_next<=0; oe<=0; m_count<=0; act_ref_req<=0; end else case(m_state) // idle 0: if(init_done) begin if(ref_req==1) begin m_state<=6; end else begin m_state<=1; end end // row active 1: begin m_state<=2;m_cmd<=4'b0011; oe <= 1'b0;bank<=m_bank;addr<=m_bus_addr[20:9]; m_next<=wr?3:4; m_count<=2;//*********************** tRC end //NOP 2:begin oe <= 1'b0;act_ref_req<=0;if (m_next == 7) m_cmd <= {{1{1'b0}},3'h7}; else m_cmd <= {{{1'b0}},3'h7}; if (m_count > 1) m_count <= m_count - 1'b1; else m_state <= m_next; end //read 3:begin m_cmd <= {{{1'b0}},3'h5}; oe <= 1'b0; if (ref_req) begin m_state <= 6; end else begin addr <= {4'b0100,m_bus_addr[7:0]}; out_data <= dq; m_state <=2; m_next<=1; m_count<=2; end end //write 4:begin m_cmd <= {{{1'b0}},3'h4}; if (ref_req) begin m_state <= 6; end else begin addr <={4'b0100,m_bus_addr[7:0]}; m_state <=2; m_next<=1; oe <= 1'b1; end end //ref 6:begin oe <= 1'b0; m_state <= 7; //*********************************************tRP addr <= {12{1'b1}};// // precharge all if arf, else precharge csn_decode if (ref_req) m_cmd <= {{1{1'b0}},3'h2}; else m_cmd <= {{{1'b0}},3'h2}; end // ref_act 7:begin act_ref_req <= 1'b1; m_state <= 2; m_cmd <= {{1{1'b0}},3'h1}; m_count <= 3; m_next <= 0; end default: begin m_state <= m_state; m_cmd <= 4'b1111; oe <= 1'b0; end // default endcase end endmodule |
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