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上海交通大学与都柏林大学联合培养-边缘传感器低功耗深度神经网络博士招聘啦！(带研究
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PhD Research Scholarship in Low-Power Deep Neural Networks for Edge Sensors Host Institution: University College Dublin/ Trinity College Dublin, Ireland Collaborator Institution: Shanghai Jiao Tong University, China. Research Advisors: Dr. Shreejith Shanker (TCD), Dr. Li Yongfu (SJTU), Dr. Deepu John (UCD) Scholarship: Full Tuition Fee waiver (by UCD/TCD) + 16200 Euro/Year Stipend (CSC) Research Topic & Background This project will investigate novel DNN techniques for time-series data and its hardware implementation. The project will address the challenges of implementing complex DNN models for energy efficient and performance driven IoT edge devices. The project aims to develop hardware architectures that are scalable, and easily adaptable to different DNN models and applications. The DNN architectures developed will be demonstrated in hardware for a wearable healthcare application such as heartbeat identification. In traditional systems, the data generated in IoT devices are sent to cloud servers over wireless networks. AI and deep learning techniques are employed on servers for data processing and analytics. Due to the large amount of data generated in these sensors, it is beneficial (for system power, bandwidth) to process this data locally at the IoT node and send the inference to the cloud instead. In this project, we plan to 1) develop DNNs specifically targeted for time-series data using 1D convolution 2) develop circuit architectures that are scalable and programmable 3) verify the entire system on an FPGA/ASIC. For developing the DNN model, a connected health use case of heartbeat identification from biomedical data will be used. The hardware will be implemented such that it is scalable and programmable to support other applications as well. For reducing the complexity of DNN hardware, we plan to use a combination of algorithmic and circuit approaches such as 1) optimizing the DNN topology 2) applying network pruning technique 3) quantization 4) optimizing memory access schemes The project will involve collaboration with multi-disciplinary researchers who are working on analog & mixed signal design, low power circuit design and Edge computing, machine learning etc. The position also provides the opportunity to gain valuable experience in design, fabrication of circuits. The successful candidate will get opportunities for presenting their work in international conferences, and publication of the research in high impact journals. Applicants for this position should ideally have: • A first-class honors BE/ME degree in: Electrical /Electronic Engineering or equivalent. • Strong analytical skills and good knowledge in Verilog/VHDL, Matlab/Python. • Knowledge / background in digital circuit design, synthesis, machine learning, FPGA design. • Good interpersonal, communication and English language skills (IELTS/Toefl needed). • Be enthusiastic and willing to learn new concepts and ideas. Enquires Applicants can email to Assoc. Prof. Li Yongfu @ Yongfu.li@sjtu.edu.cn to understand the program better. How to Apply Applications consisting of a cover letter, Transcripts, contact details of 3 referees, and curriculum vitae should be sent to deepu.john@ucd.ie at the earliest latest by Jan 30th, 2022 [ 来自版块群 上海 ] |
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